/*
 * Copyright 2022 Rich yang, 18158898020@189.com
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     https://www.apache.org/licenses/LICENSE-2.0
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied,
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */


module inst_rom(
    input  wire      ce,
    input  wire[`InstAddrBus] addr,
    output reg[`InstBus] inst
);

  reg[`InstBus] inst_mem[0:`InstMemNum-1];

  initial $readmemh("inst_rom.data", inst_mem);

  always @ (*) begin
    if (ce == `ChipDisable) begin
      inst <= `ZeroWord;
    end else begin
      inst <= inst_mem[addr[`InstMemNumLog2+1:2]];
    end
  end

endmodule
